A bit line sense amplifier is commonly used in a memory device such as a flash memory device for determining bit data stored in a memory cell. FIG. 1 shows an example prior art bit line sense amplifier (BLSA) 100 as disclosed in U.S. Pat. No. 5,701,268 to Lee et al.
The BLSA 100 includes first and second PMOSFETs (P-channel metal oxide semiconductor field effect transistors) MP1 and MP2 and first and second NMOSFETs (N-channel metal oxide semiconductor field effect transistors) MN1 and MN2, connected to form a latch. The drains of the PMOSFET MP1 and the NMOSFET MN1 are connected together at a bit line BL, and the drains of the PMOSFET MP2 and the NMOSFET MN2 are connected together at a complementary bit line BLB.
The sources of the PMOSFETs MP1 and MP2 are connected together at a first biased node LA, and the sources of the NMOSFETs MN1 and MN2 are connected together at a second biased node LAB. The gates of the PMOSFET MP1 and the NMOSFET MN1 are connected together to the complementary bit line BLB. The gates of the PMOSFET MP2 and the NMOSFET MN2 are connected together to the bit line BL.
A biasing PMOSFET MP3 is connected between a high voltage source providing a high voltage VINTA and the first biased node LA. The gate of the biasing PMOSFET MP3 is controlled by a high bias control signal LAPG. A biasing NMOSFET MN3 is connected between a low voltage source providing a low voltage VSSA such as a ground node and the second biased node LAB. The gate of the biasing NMOSFET MN3 is controlled by a low bias control signal LANG.
Further in the BLSA 100 of FIG. 1, NMOSFETs MN4, MN5, and MN6 are connected between the bit line BL and the complementary bit line BLB for pre-charging and equalizing such nodes BL and BLB. The drains of the NMOSFETs MN5 and MN6 are connected to a bit line bias voltage source providing a bit line voltage VBL. The source of the NMOSFET MN5 is connected to the bit line BL, and the source of the NMOSFET MN6 is connected to the complementary bit line BLB.
The drain of the NMOSFET MN4 is connected to the bit line BL, and the source of the NMOSFET MN4 is connected to the complementary bit line BLB. The gates of the NMOSFETs MN4, MN5, and MN6 are controlled by a pre-charge and equalization control signal PEQI. The NMOSFETs MN4, MN5, and MN6 are turned on for simultaneously pre-charging and equalizing the bit line BL and the complementary bit line BLB to the bit line voltage VBL.
In the BLSA 100, the first biased node LA is floating with no current flowing through such a node LA in a non-access mode when a memory cell is not being accessed by being connected to the bit line BL. However, noise at the bit line BL may turn on the NMOSFET MN2 to lower the voltage at the second biased node LAB. Such a voltage change may disadvantageously result in inaccurate sensing at the bit line BL and the complementary bit line BLB.
FIG. 2 shows another example prior art bit line sense amplifier (BLSA) 102 as disclosed in U.S. Pat. No. 6,859,405 to Lee et al. The BLSA 102 of FIG. 2 includes the PMOSFETs MP1 and MP2 and the NMOSFETs MN1 and MN2 connected to each-other as a latch similarly as described in reference to FIG. 1. In addition, the BLSA 102 also includes the biasing PMOSFET MP3 and the biasing NMOSFET MN3 similarly configured as described in reference to FIG. 1.
However in contrast to FIG. 1, the BLSA 102 of FIG. 2 includes NMOSFETs MN7, MN8, and MN9 connected between the first and second biased nodes LA and LAB for pre-charging and equalizing the bit line BL and the complementary bit line BLB. The NMOSFETs MN7, MN8, and MN9 are turned on for simultaneously pre-charging and equalizing the first and second biased nodes LA and LAB to the bit line voltage VBL.
The BLSA 102 includes four MOSFETs MP3, MN8, MN9, and MN3 between the high and low voltages VINTA and VSSA. Thus with a low voltage range between VINTA and VSSA, the BLSA 102 may not operate with high speed. In addition, the bit line voltage VBL may deviate from a desired level of ½ VDD resulting in incorrect sensing at the bit line BL and the complementary bit line BLB. Furthermore, the speed and accuracy of operation of the BLSA 102 may also be disadvantageously influenced by use of the high and low bias control signals LAPG and LANG.